Alphawave Semi Leads the Way with Successful Tapeouts of HBM3 and UCIe IP on TSMC’s 3nm Process
Alphawave Semi, a global leader in high-speed connectivity for technology infrastructure, has announced the successful tapeouts of its High Bandwidth Memory 3 (HBM3) PHY and Universal Chiplet Interconnect Express (UCIe) PHY IPs on TSMC’s most advanced 3nm process. This achievement paves the way for the development of chiplet-enabled silicon platforms tailored for hyperscale and data infrastructure customers.
One of the notable accomplishments is Alphawave Semi’s status as the first company to announce UCIe PHY IP supporting faster die-to-die data rates of 24Gbps per lane, delivering an impressive bandwidth of 7.9 Terabits per second over just a millimeter of a chip’s surface. This breakthrough in connectivity enables the transfer of data at unprecedented speeds while optimizing chip space utilization.
The demand for advanced chips capable of handling the exponential surge in AI-generated data has necessitated the development of cutting-edge chiplet-enabled silicon platforms. Alphawave Semi’s 3nm custom silicon platform is built on flexible and customizable connectivity IP, allowing customers to integrate advanced interfaces such as CXL, UCIe, HBMx, and Ethernet onto their custom chips and chiplets.
In the realm of AI and high-performance computing, memory bandwidth is a critical performance indicator. HBM3 emerges as the top choice, offering the highest bandwidth, optimal area footprint, and superior power efficiency. Alphawave Semi’s HBM3 PHY IP targets high-performance memory interfaces, boasting speeds of up to 8.6Gbps and 16 channels, all while operating at low power. The integration of HBM PHY with a configurable JEDEC-compliant HBM controller allows customers to maximize efficiency for AI and high-performance computing workloads.
Chiplets, with their advantages including flexibility, scalability, power efficiency, and cost-effectiveness, are poised to dominate the world of high-performance data center AI semiconductors. Alphawave Semi’s UCIe PHY IP, designed to connect chiplet silicon die in the same package, supports speeds of up to 24Gbps per wire while consuming less than 0.3 picoJoules of power per bit. This extremely power-efficient, low-latency, and highly reliable interface IP can be paired with PCIe, CXL, and streaming controllers to support the full UCIe protocol stack. Supporting advanced packaging options like TSMC’s Chip-on-Wafer-on-Substrate and Integrated Fan-Out, the UCIe PHY offers greater signal densities and more cost-effective solutions.
Excitement surrounds the announcement of Alphawave Semi’s 3nm tapeouts, showcasing the company’s dedication to technology leadership in connectivity and fostering an open chiplet ecosystem. With the development of a comprehensive 3nm chiplet connectivity platform, hyperscalers and data infrastructure customers now have the flexibility and scalability needed to keep up with the demands of data-intensive applications like generative AI.
Industry leaders have also expressed their enthusiasm for Alphawave Semi’s achievements. Praveen Vaidyanathan, Vice President and General Manager of Micron’s Compute Products Group, highlights the impact of Alphawave Semi’s HBM3 solution on AI workloads in data centers. Dr. Debendra Das Sharma, Chairman of the UCIe Consortium, recognizes the contribution of Alphawave Semi’s 24Gbps/lane UCIe IP in fueling innovation through leading-edge chiplet connectivity.
With its commitment to advancing the critical data infrastructure of the digital world, Alphawave Semi continues to push the boundaries of high-speed connectivity. By leveraging its expertise in semiconductor IP and delivering innovative solutions, Alphawave Semi is poised to shape the future of technology infrastructure.
